1. Field of the Invention
The present invention relates to a semiconductor storage device having a memory cell array composed of dynamic random access memory (DRAM) and a timer for executing refresh operation according to a timer period.
2. Description of a Related Art
As more features and functions are implemented in mobile devices such as cellular phones, a demand for higher capacity random access memory (RAM) is rapidly growing.
Thus, there arises a need for using RAM with high capacity and low current consumption instead of conventionally used asynchronous static random access memory (SRAM) with relatively low current consumption. To meet this need, asynchronous pseudo-SRAM (PSRAM) that combines the best properties of the asynchronous SRAM for easy system design and DRAM for easy capacity increase is increasingly used for mobile devices (see Japanese Unexamined Patent Application Publication 2003-85970). The asynchronous PSRAM is a semiconductor storage device of which memory cell array is composed of DRAM cells and which has an asynchronous SRAM external interface.
FIG. 15 is a block diagram showing the conventional semiconductor storage device described in the above conventional art. This conventional semiconductor storage device has a memory cell array 5 for storing data. The memory cell array 5 is an array of areas having a DRAM cell, and it is a collection of capacitor cells. A chip select signal /CS is an external signal to control the semiconductor storage device. If the external signal /CS is High, the semiconductor storage device is in stand-by mode; if it is Low, the device is in normal operation mode for data reading or writing.
The semiconductor storage device also has a refresh request signal generation timer 1. The refresh request signal generation timer 1 automatically sets a refresh request signal RFR to High at such a period as to allow the memory cell array 5 to retain data. The external signal /CS and the refresh request signal RFR are input to an AND circuit 9. The AND circuit 9 generates High level of output signal E when the external signal /CS is High; thus the device is in stand-by mode, and the refresh request signal RFR is High.
The output signal E of the AND circuit 9 is input to a control signal generation block 2, which serves as a refresh operation unit. The control signal generation block 2 outputs High level of refresh control signal D when the output signal E from the AND circuit 9 is High. On the other hand, the external signal /CS is input to a control signal generation block 3. The control signal generation circuit 3 outputs High level of read/write control signal C when the external signal /CS is Low and the device is in the normal operation mode.
The refresh control signal D and the read/write control signal C are input to a memory cell array control signal generation block 4. The memory cell array control signal generation block 4 outputs a memory array core control signal MCC to the memory cell array 5 when the refresh control signal D is High or the read/write control signal C is High so as to perform refresh operation or read/write operation in the memory cell array 5.
The semiconductor storage device also has a refresh address 7, a multiplexer MUX 8, and a data input/output buffer 6. The refresh address 7 receives the refresh control signal D and outputs addresses A0 to Am to the multiplexer 8 when the refresh control signal D is High. The multiplexer 8 receives the refresh control signal D, the addresses A0 to Am, and external signals ADD0 to ADDm. In the refresh operation mode when the refresh control signal D is High, the multiplexer 8 sequentially selects each address from the addresses A0 to Am and outputs the addresses as signals B0 to Bm to the memory cell array 5 so as to perform the refresh operation in the cells of the memory cell array 5 specified by the signals B0 to Bm. In the read/write operation mode when the refresh control signal D is Low, on the other hand, the multiplexer 8 selects each address from the external signals ADD0 to ADDm and outputs the addresses as signals B0 to Bm so as to perform the read/write operation in the cells specified by the signals B0 to Bm. Further, in the read operation, the data input/output buffer 6 receives data DATA0 to DATAn output from the memory cell array 5, buffers the data, and outputs the data as external signals DQ0 to DQn. In the write operation, on the other hand, the buffer 6 receives external signals DQ0 to DQn from outside, buffers the signals, and outputs them as data DATA0 to DATAn to the memory cell array 5.
The operation of the conventional semiconductor storage device is explained below. FIGS. 16A and 16B are timing charts showing the operations of the above conventional semiconductor storage device and another conventional semiconductor storage device, which is described later, respectively. First, the refresh operation is explained. The external signal /CS is High and the device is thus in stand-by mode. In this state, the refresh signal generation timer 1 generates a refresh request signal RFR. Since the external signal /CS is High and the refresh request signal is also High, the output signal E of the AND circuit 9 is High. The control signal generation block 2 thereby outputs High level of refresh control signal D. Then, the memory cell array control signal generation block 4 outputs High level of memory array core control signal MCC, the refresh address 7 outputs addresses A0 to Am to be refreshed, and the multiplexer 8 sequentially selects the addresses A0 to Am and outputs signals B0 to Bm to the memory cell array 5. The refresh operation is thereby performed in the cells of the memory cell array 5 specified by the signals B0 to Bm.
The read operation is explained below. The read operation is performed during the normal operation mode where the external signal /CS is Low. Thus, the output signal E of the AND circuit 9 is always Low not to perform the refresh operation. The control signal generation block 3 outputs a read control signal C to the memory cell array control signal generation block 4 and the memory cell array 5. The memory cell array control signal generation block 4 thereby outputs High level of memory array core control signal MCC. In this state, external signals ADD0 to ADDm are input to the multiplexer 8, which then sequentially selects each signal from the external signals ADD0 to ADDm and outputs them as signals B0 to Bm to the memory cell array 5. The read operation is thereby performed in the cells of the memory cell array 5 specified by the signals B0 to Bm. The read data is input as DATA0 to DATAn to the data input/output buffer 6, which buffers and outputs the data as external signals DQ0 to DQn.
The write operation is explained below. The write operation is also performed during the normal operation mode where the external signal /CS is Low. The control signal generation block 3 outputs a write control signal C to the memory cell array control signal generation block 4 and the memory cell array 5. The memory cell array control signal generation block 4 thereby outputs High level of memory array core control signal MCC. In this state, external signals ADD0 to ADDm are input to the multiplexer 8, which then sequentially selects each signal from the external signals ADD0 to ADDm and outputs them as signals B0 to Bm to the memory cell array 5. At the same time, external signals DQ0 to DQn are input to the data input/output buffer 6, which buffers and outputs the data as data DATA0 to DATAn to the memory cell array 5. The data DATA0 to DATAn is thereby written to the cells of the memory cell array 5 specified by the signals B0 to Bm. The memory array core control signal MCC is High in the read and write operations.
It is impossible to perform the refresh operation and the read/write operation in parallel. In a general DRAM cell array, it is impossible to perform a sequence of operations of word selection, destructive data reading, data amplification, data writing, and word unselection in parallel on one area.
FIG. 16A shows the operation waveform of the conventional semiconductor storage device performing the refresh operation and the read operation successively. In this example, the external signal /CS is High in the initial state. The refresh request signal RER is generated, which is, turned to High, at a constant period regardless of an external state. Thus, the output signal E can be generated (turned to High) in all the period when the external signal /CS is High, which is, the period corresponding to the shaded area in FIG. 16A. If the output signal E becomes High in the posterior edge of the shaded area, immediately before the external signal /CS changes from High to Low, the refresh control signal D changes from Low to High accordingly, thereby starting the refresh operation. The memory array core control signal MCC stays High during the refresh operation. Thus, the read operation cannot be started until the refresh operation ends. After the refresh operation ends and the refresh control signal D changes from High to Low, the read control signal C changes from Low to High, starting the read operation. The memory array core control signal MCC stays High during the read operation. In this way, since the device cannot start the read operation until the refresh operation is over, it is necessary to wait for a time period indicated by A0 in FIG. 16A, at maximum, after the external signal /CS changes to Low until the read operation is started.
As described above, the conventional semiconductor storage device shown in FIG. 15 has a problem that, when performing the read operation after the refresh operation, there can be a considerable wait time before starting the read operation depending on timing to start the refresh operation.
Since more and more features and functions will be implemented, semiconductor storage devices should be capable of not only higher density packaging but also higher speed read/write operation. However, such semiconductor storage devices as shown in FIG. 15 are incapable of the high speed operation since the start of the read operation delays due to the refresh operation.
One solution for achieving the high speed read/write operation in the conventional semiconductor storage device shown in FIG. 15 is to apply a general synchronization technique. FIG. 17 is a block diagram showing a semiconductor storage device to which synchronization is applied to enhance high speed operation. In this semiconductor storage device, the same elements as in the semiconductor storage device of FIG. 15 are denoted by the same reference symbols and redundant description is omitted. This semiconductor storage device is different from the semiconductor storage device of FIG. 15 in the part enclosed by a frame 11 in FIG. 17. This semiconductor storage device has a clock input buffer 10 to receive a clock signal CLC from outside, generate an internal clock signal INCLK based on the input clock signal CLK, and output INCLK toward the control signal generation blocks 2 and 3. Except for this, the structure of this semiconductor storage device is the same as that of the semiconductor storage device shown in FIG. 15.
The operation of the semiconductor storage device shown in FIG. 17 is explained hereinafter. A clock signal CLK is input to the clock input buffer 10 from outside. The clock input buffer 10 buffers the clock signal CLK to generate an internal clock signal INCLK and outputs INCLK to the control signal generation blocks 2 and 3. If the external signal /CS is High and the refresh request signal RFR is also High, the control signal generation block 2 generates a refresh control signal D, that is, sets the refresh control signal D to High in synchronization with the internal clock signal INCLK, thereby starting the refresh operation in the memory cell array 5. If, on the other hand, the external signal /CS is Low, the control signal generation block 3 generates a read/write control signal C, that is, sets the read/write control signal C to High in synchronization with the internal clock signal INCLK, thereby starting the read/write operation in the memory cell array 5.
FIG. 16B shows the operation waveform of this conventional synchronized semiconductor storage device performing the refresh operation and the read operation successively. In this example, the external signal /CS is High in the initial state. The refresh request signal RER becomes High at a constant period regardless of an external state. Thus, the output signal E can become High in all the period when the external signal /CS is High, which is, the period corresponding to the shaded area in FIG. 16B.
This semiconductor storage device synchronizes the refresh control signal D with the internal clock signal INCLK in the control signal generation block 2. Thus, if the refresh request signal RFR becomes High and the output signal E thereby becomes High after the internal clock signal INCLK rises for the last time in the period when the external signal /CS is High, which is, the period corresponding to the shaded area in FIG. 16B, the refresh control signal D does not rise, not starting the refresh operation. In other words, the refresh operation is started only when the refresh request signal RFR becomes High before the internal clock signal INCLK rises for the last time. Hence, as shown in FIG. 16B, a wait time from High to Low change in the external signal /CS to the start of read operation starts is A1 at maximum. Comparing FIGS. 16A and 16B, the wait time A1 in the synchronization operation is shorter than the wait time A0 in the non-synchronization operation. This is the same when performing the write operation after the refresh operation.
In this way, by applying a general synchronization technique to the conventional semiconductor storage device, it is possible to reduce the wait time by the length of A2=A0−A1 to speed up the read/write operation. If the refresh request signal RFR becomes High after the last time the internal clock signal INCLK rises, the refresh operation is not performed in this timing but is postponed until the next time. The period of the refresh operation is about 50 μs (microseconds), for example, and the period to require the refresh operation in DRAM is about 100 ms (milliseconds) at maximum, for example. Thus, data stored in the memory cell array is not erased even if the refresh operation is postponed once.
The synchronized semiconductor storage device shown in FIG. 17, however, has a problem that the higher speed operation by the synchronization causes an increase in current consumption in stand-by mode. This semiconductor storage device generates the internal clock signal INCLK for the synchronization of the refresh operation. Thus, extra current is consumed for the operation of the internal clock signal INCLK. FIG. 18 is a timing chart showing the operation waveform of the semiconductor storage device shown in FIG. 17 in the stand-by mode when the external signal /CS is High. The refresh request signal RFR is generated about every 50 μs. As shown in FIG. 18, the internal clock signal INCLK keeps operating during the period where the refresh control signal D is not generated, consuming current.
Recently, such semiconductor storage devices as shown in FIG. 17 are often used as memory of mobile devices. In cellular phones, for example, which are typical of the mobile devices, it is extremely important to reduce the battery consumption in stand-by more to increase an operable time. Thus, a semiconductor storage device with a large capacity and low current consumption in stand-by mode and capable of high speed read/write operation is demanded for the memory in the mobile devices. Though the semiconductor storage device of FIG. 17 allows the high speed operation, it has high power consumption, as described above.
To solve this problem, a semiconductor storage device in which a clock signal is partly stopped in the stand-by mode has been proposed (see Japanese Unexamined Patent Application Publication 2002-184180, FIGS. 2 and 7, for example). According to this technique, in a synchronized DRAM, there are provided a clock input buffer to receive a clock signal from outside and distribute the clock signal to internal components, a command input buffer to input a command in synchronization with the clock signal, an address input buffer to input an address in synchronization with the clock signal, and a data input buffer to input data in synchronization with the clock signal. In data retention mode, the clock signal is supplied only to the command input buffer, not to the address input buffer and the data input buffer.
This conventional technique, however, has the following problem. Though this semiconductor storage device can stop the supply of the clock signal to the address input buffer and the data input buffer in data retention mode, it cannot stop the supply of the clock signal to the command input buffer since it is necessary to perform the refresh operation in the data retention mode, requiring the command for controlling the refresh operation. Thus, a certain amount of current is consumed in the data retention mode.
This problem will be solved if the above semiconductor storage device contains a self timer to periodically perform the refresh operation since this eliminates the need to input the command for controlling the refresh operation from outside and allows stopping the supply of the clock signal to the command input buffer. However, this structure causes delay in receiving the command when shifting from the data retention mode to the normal operation mode, as described in DATA SHEET ELPIDA 128 M bits Mobile RAM Document No. E0195E50 (Ver.5.0), P.43, tRC1 spec in the figure of Self Refresh (Entry and Exit). Consequently, the read operation delays to impede high speed operations.